1. Field of Invention
The invention relates to a design method for reducing the peak current of a clock tree. Moreover, the invention pertains to integrated circuit (IC) designs and the related electronic design automation (EDA) tools.
2. Related Art
The design of clock trees in digital chips has been previously focused on improving the chip efficiency. For example, U.S. Pat. Nos. 6,502,222 and 6,433,605 aimed at providing a clock tree with zero clock skew. The advantages of this type of designs are that the clock tree is easier to implement and that the clock analysis of the chips is simpler. However, once power consumption became an important issue in the chip design, the clock tree with a selective enable clock had been disclosed in U.S. Pat. Nos. 6,879,185 and 5,703,498. This type of techniques is to shut down the clock that is currently not operating in a timing circuit in order to reduce unnecessary dynamic power waste. This can achieve the goal of reducing the overall chip power consumption. Nevertheless, to appropriately control the clock, the entire clock tree has to be added with an additional control circuit and therefore increases the complexity in implementing the clock tree.
For a timing circuit, its peak current comprises three parts: one is the synchronous logic, another is the combinational logic, and the other is the clock tree.
To reduce the peak current of a chip, traditionally the most common method is to use the clock tree with a non-zero clock skew in order to reduce the peak current in the synchronous logic. Such a scheme was disclosed in U.S. Pat. Nos. 6,795,954 and 6,559,701. This scheme uses different clock arrival times to properly adjust the trigger time of the synchronous logic. Therefore, the current consumption of individual synchronous logics is separated to reduce the peak current.
Consequently, how to effectively reduce the peak current of a clock tree has been an intriguing topic in the field.